1. Field of Invention
This invention relates to a multi-chips stacked package. More particularly, the present invention is related to a multi-chips stacked package with an intermediate chip for preventing an upper chip from being tilted to contact electrically conductive wires and cause said wires to be damaged.
2. Related Art
Recently, integrated circuit (chip) packaging technology is becoming a limiting factor for the development in packaged integrated circuits of higher performance. Semiconductor package designers are struggling to keep pace with the increase in pin count, size limitations, low profile, and other evolving requirements for packaging and mounting integrated circuits.
Due to the assembly package in miniature and the integrated circuits operation in high frequency, MCM (multi-chips module) packages are commonly used in said assembly packages and electronic devices. Usually, said MCM package mainly comprises at least two chips encapsulated therein, for example a processor unit, a memory unit and related logic units, so as to upgrade the electrical performance of said assembly package. In addition, the electrical paths between the chips in said MCM package are short so as to reduce the signal delay and save the reading and writing time.
Generally speaking, conventional MCM packages shall be a multi-chips side-by-side package or a multi-chips stacked package. As shown in FIG. 1, it illustrates a multi-chips stacked package patented in U.S. Pat. No. 5,323,060 to Rich Fogal et al. entitled “Multichip Module Having a Stacked Chip Arrangement” and said stacked package mainly comprises a substrate 110, a lower chip 120 and an upper chip 130. Therein, the upper chip 130 is disposed on the lower chip 120 by wire-bonding and chip-stacking technology, and electrically connected to the substrate 110. Specifically, the U.S. Pat. No. 5,323,060 is characterized in that an adhesive layer 140 is interposed between the lower chip 120 and the upper chip 130 so as to provide a clearance or a gap for wires 150 bonding the lower chip 120 to the substrate 110. Namely, the bonding wires 150 can be accommodated in the clearance or the gap. In addition, the thickness of the adhesive layer 140 shall be larger than the distance between the active surface of the lower chip 120 and the loop height of the bonding wires 150 so as to prevent the upper chip 130 contacting the wires 150. Generally speaking, the adhesive layer 140 is epoxy or tape. However, it is difficult to provide a uniform adhesive layer with an eight (8) mils thickness. It should be noted that when the upper chip 130 is larger than the lower chip 110 in size and the upper chip is electrically connecting to the substrate 110 via wires 150, the upper chip 130 is tilted to contact the wires 150 so as to cause the wires 150 to be damaged due to larger wire-bonding force and the difficulty in controlling the thickness of the adhesive layer 140.
Accordingly, another multi-chips stacked package is provided as shown in FIG. 2. Said package is characterized in that an intermediate chip 160 is interposed between the lower chip 120 and the upper chip 140 through two adhesive layers 162 and 164. The adhesive layers 162 and 164 are made of thermosetting epoxy. Although, the intermediate chip 160 can define a clearance to provide the lower chip 162 enough space for wire-bonding the lower chip 162 to the substrate 110. However, when the bonding wires 150 are bonded the upper chip 130 to the substrate 110 by a larger wire-bonding force, not only the adhesive layer 164 between the upper chip 130 and the intermediate chip 160 but also the adhesive 162 between the lower chip 120 and the intermediate chip 160 is more difficult to control. Accordingly, the upper chip 130 will be more easily tilted so as to cause the wires 150 for connecting the lower chip 120 and the substrate 110 to be damaged.
Therefore, providing another assembly package to solve the mentioned-above disadvantages is the most important task in this invention.